A DC-DC converter of multi-output type comprises a switching element and a resonance circuit provided on a primary side of a transformer to turn on and off the switching element in order to produce a plurality of outputs from a plurality of secondary windings of transformer through rectifying smoothers. Such DC-DC converters have been widely applied to inexpensive power sources for information processing appliances such as personal computers, and household electric appliances such as air-conditioners or audio or visual equipments.
For example, a prior art DC-DC converter of multi-output type shown in FIG. 1 comprises first and second primary MOS-FETs 2 and 3 as first and second primary switching elements connected in series to a DC power source 1; a series circuit which includes a capacitor 4, an inductance 5d and a primary winding 5a of a transformer 5 connected in series to one another and in parallel to second primary MOS-FET 3; a pseudo voltage resonance capacitor 6 connected between drain and source terminals of first primary MOS-FET 2; a first rectifying smoother 9 which includes a first output rectifying diode 7 and a first output smoothing capacitor 8; a first output voltage detector 12 for outputting an error signal VE1, a difference between first DC output voltage VO1 and a limitary reference voltage (not shown) for regulating a value of first output voltage VO1; a primary control circuit 14 for controlling the on-off operation of first and second primary MOS-FETs 2 and 3 based on error signal VE1 forwarded from first output voltage detector 12 to an input terminal FB of primary control circuit 14 as a feedback signal through light emitter 13a and light receiver 13b of a photocoupler 13; a second rectifying smoother 17 which includes a second output rectifying diode 15 and an output smoothing capacitor 16; an output control MOS-FET 20 as a secondary switching element connected between second output rectifying diode 15 and a second output smoothing capacitor 16 of second rectifying smoother 17; and a secondary control circuit 21 for controlling the on-off operation of output control MOS-FET 20 based on second output voltage VO2 from second rectifying smoother 17. A first secondary winding 5b of transformer 5 is connected between first output rectifying diode 7 and smoothing capacitor 8 so that first rectifying smoother 9 produces a first DC output voltage VO1 from first output terminals 10 and 11. A second secondary winding 5c of transformer 5 is connected between second output rectifying diode 15 and smoothing capacitor 16 so that second rectifying smoother 17 produces a second DC output voltage VO2 from second output terminals 18 and 19.
As shown in FIG. 2, transformer 5 comprises a pair of E-shaped core halves 5g and 5h formed of magnetic sintered compact such as ferrite, each core half 5g, 5h having a pair of outer legs 5i and 5j and an intermediate leg 5k; a plastic bobbin 5l formed with a cylindrical portion 5m and a pair of flanges 5n at the opposite ends of cylindrical portion 5m; insulating barrier tapes 5p wound around bobbin 5l adjacent to flanges 5n; primary winding 5a and first and second secondary windings 5b and 5c concentrically wound around intermediate legs 5k of core halves 5g and 5h between barrier tapes 5p; and insulating tapes 5q for electrically insulating between primary winding 5a and first secondary windings 5b and between primary winding 5a and second secondary winding 5c. Intermediate legs 5k of E-shaped core halves 5g and 5h are positioned in cylindrical portion 5m of bobbin 5l. Primary, first and second secondary windings 5a, 5b and 5c are coaxially wound in the form of a layered structure around cylindrical portion 5m of bobbin 5l in the outward order of primary, second and first secondary windings 5a, 5c and 5b. Insulating tape 5q is inserted between primary and second secondary windings 5a and 5c to form a fully or slightly electromagnetic sparse coupling between primary and first secondary winding 5a and 5b and between primary and second secondary winding 5a and 5c while forming electromagnetic close coupling between first and second secondary windings 5b and 5c wound adjacent to each other. As a result, this arrangement causes transformer 5 of FIG. 2 to have a leakage inductance 5d connected equivalently and in series to primary winding 5a, and an excitation inductance 5e connected equivalently and in parallel to primary winding 5a, while leakage inductance 5d serves as a coil or reactor for current resonance.
As shown in FIG. 3, primary control circuit 14 comprises an oscillation circuit 22 for producing pulse signals VPL; an inverter 23 for generating inverted signals −VPL of pulse signals VPL from oscillation circuit 22; a first generator 24 for adding constant dead time to pulse signals VPL from oscillation circuit 22 to provide first drive signals VG1; a low side buffer amplifier 25 for applying first drive signals VG1 from first generator 24 to a gate terminal of first primary MOS-FET 2; a second generator 26 for adding constant dead time to pulse signals −VPL from inverter 23 to produce second drive signals VG2; a level shifter 27 for adjusting the voltage level of second drive signals VG2; and a high side buffer amplifier 28 for applying second drive signals VG2 from level shifter 27 to a gate terminal of second primary MOS-FET 3. Oscillation circuit 22 receives error signals VE1 at input terminal FB as feedback signals from first output voltage detector 12 through photocoupler 13 to produce pulse signals VPL which has a constant pulse width and frequency variable in response to voltage level of error signals VE1 from first output voltage detector 12. Accordingly, primary control circuit 14 forwards first and second drive signals VG1 and VG2 to each gate terminal of first and second primary MOS-FETs 2 and 3, while first drive signals VG1 have the fixed or constant on-period of time and the off-period of time variable based on voltage level of error signals VE1 from first output voltage detector 12, and second drive signals VG2 have the fixed or constant off-period of time and the on-period of time variable based on voltage level of error signals VE1 from first output voltage detector 12 to alternately turn first and second primary MOS-FETs 2 and 3 on and off in response to voltage level of error signal VE1 from first output voltage detector 12. Specifically, primary control circuit 14 changes the on-period of second primary MOS-FET 3 based on first output voltage VO1 from first rectifying smoother 9 to control the on-duty of first primary MOS-FET 2 while maintaining the on-period of first primary MOS-FET 2 fixed.
As shown in FIG. 4, second control circuit 21 comprises a timing detector 29 for sensing a winding voltage VT22 produced on second secondary winding 5c of transformer 5 to produce detection signals VTD when first primary MOS-FET 2 is turned on; a second output voltage detector 30 for sensing a second output voltage VO2 applied on a second output smoothing capacitor 16 of a second rectifying smoother 17 to produce an error signal VE2, a difference between the second output voltage VO2 and a limitary reference voltage (not shown) for regulating the value of second output voltage VO2; a PWM (Pulse Width Modulation) controller 31 driven by detection signals VTD from timing detector 29 for controlling occurrence cycle of pulse array signals VPT based on error signal VE2 from second output voltage detector 30; an RS flip flop 32 which is set by detection signal VTD from timing detector 29 and reset by pulse array signal VPT from PWM controller 31; and a drive circuit 33 for forwarding a second drive signal VS2 to a gate terminal of output control MOS-FET 20 when RS flip flop 32 produces the output signal. Thus, output control MOS-FET 20 is synchronously turned on and off with switching frequency or on-period of first primary MOS-FET 2 to control on-period of output control MOS-FET 20 based on second output voltage VO2 from second output smoothing capacitor 16 of second rectifying smoother 17.
In operation of DC-DC converter shown in FIG. 1, a main switch not shown is turned on to supply electric power to primary control circuit 14 which is therefore activated to provide first and second drive signals VG1 and VG2 for gate terminals of first and second primary MOS-FETs 2 and 3 which start to be alternately turned on and off. When first primary MOS-FET 2 is turned on, winding current IQ1 flows from DC power source 1 through current resonance capacitor 4, leakage inductance 5d and primary winding 5a of transformer 5, first primary MOS-FET 2 and DC power source 1. Winding current IQ1 can roughly be divided into three kind of currents, namely first and second load currents and excitation current. First load current flow passes through current resonance capacitor 4, leakage inductance 5d and primary winding 5a of transformer 5, first primary MOS-FET 2 to induce first secondary current ID1 flowing through first secondary winding 5b of transformer 5, first output rectifying diode 7 and first output capacitor 8 of first rectifying smoother 9. Second load current flow runs through current resonance capacitor 4, leakage inductance 5d and primary winding 5a of transformer 5 and first primary MOS-FET 2 to lead second secondary current ID2 to flow through second secondary winding 5c of transformer 5, second output rectifying diode 15 and second output smoothing capacitor 16 of second rectifying smoother 17. Excitation current flow goes through current resonance capacitor 4, leakage and excitation inductances 5d and 5e of transformer 5 and first primary MOS-FET 2 to accumulate magnetic energy in transformer 5 by electric energy supplied from leakage and excitation inductances 5d and 5e. Both of first and second load currents ID1 and ID2 are sine resonance currents of each resonance frequency determined by capacitance of current resonance capacitor 4 and leakage inductance 5d of transformer 5. Excitation current is a resonance current of resonance frequency determined by composite inductance of leakage and excitation inductances 5d and 5e and capacitance of current resonance capacitor 4 so that excitation current is observed as triangle waveform currents whose wave legs are formed by a part of sine wave while resonance frequency is lower than that produced during the on-period of first MOS-FET 2.
Thereafter, when first primary MOS-FET 2 is turned off, magnetic energy accumulated in transformer 5 triggers a voltage pseudo resonance between voltages VQ1 and VQ2 respectively across first and second primary MOS-FETs 2 and 3 with the resonance frequency determined by the composite inductance of leakage and excitation inductances 5d and 5e and capacitance by pseudo resonance capacitor 6. Specifically, winding current IQ1 flows through first primary MOS-FET 2 turned on, however, the moment MOS-FET 2 is turned off, winding current IQ1 is diverted toward capacitor 6. When capacitor 6 is charged by diverted winding current IQ1 up to voltage level E of DC power source 1, winding current IQ1 further is diverted to an inner diode not shown in second primary MOS-FET 3. In other words, magnetic energy stored in transformer 5 by excitation current is discharged in the form of diverted winding current which flows through inner diode of MOS-FET 3 and capacitor 4 to charge capacitor 4. Accordingly, during the charging period of time for capacitor 4 by diverted winding current, it is possible to attain the turning-on or zero voltage switching (ZVS) of MOS-FET 3.
When full excitation current flows to finish discharge of magnetic energy stored in transformer 5, electric charge accumulated in capacitor 4 causes discharge current to flow from capacitor 4 through second primary MOS-FET 3, excitation and leakage inductances 5e and 5d to capacitor 4 to release electric charge from capacitor 4. This discharge current provides an adverse excitation current flowing through transformer 5 in the opposite direction to that of winding current IQ1 flowing during the on-period of first primary MOS-FET 2. The adverse excitation current serves as a resonance current which has the resonance frequency determined by composite inductance of leakage and excitation inductances 5d and 5e and capacitance of current resonance capacitor 4. As this resonance frequency is lower than that produced during the on-period of first MOS-FET 2 so that excitation current is observed as triangle waveform current which is a cyclic current flowing through a path of capacitor 4, MOS-FET 3, excitation and leakage inductances 5e and 5d and capacitor 4.
FIG. 5(A) to 5(D) indicate waveforms of voltage VQ1 between drain and source terminals of MOS-FET 2, winding current IQ1 passing through MOS-FET 2 and voltage VC2 produced across capacitor 4. In detail, FIGS. 5(A) and 5(B) show waveforms of voltages VQ1 and VC2 and winding current IQ1 produced in case of respectively low and high input voltage level E from DC power source 1 with the fixed on-period of MOS-FET 2 and the varied on-period of MOS-FET 3. In other words, FIGS. 5(A) and 5(B) demonstrate the on-duty of first primary MOS-FET 2 controlled by varying the on-period of second primary MOS-FET 3 in response to input voltage level E on the primary side and first DC output voltage VO1 on the secondary side controlled by varying voltage VC2 produced across current resonance capacitor 4. FIGS. 5(C) and 5(D) show waveforms of voltages VQ1 and VC2 and winding current IQ1 when electric load (not shown) is respectively light and heavy. Specifically, FIG. 5(C) represents generally triangular waveform of winding current IQ1 through MOS-FET 2 under the light load condition while almost no resonance or load current flows, on the contrary, FIG. 5(D) represents winding current IQ1 through MOS-FET 2 with the partial variation into sine wave while resonance or load current flows. Also, FIGS. 5(C) and 5(D) show that the on-period of first primary MOS-FET 2 is observed when voltage VQ1 between drain and source terminals of MOS-FET 2 is at the zero level and that the on-period of first primary MOS-FET 2 does not almost change throughout the light and heavy load conditions to supply electric power from the primary to the secondary side of transformer 5 although load on the secondary side fluctuates, since the on-period of first primary MOS-FET 2, namely the period for supplying electric power from the primary to the secondary side of transformer 5 is determined by resonance frequency given by capacitance of capacitor 4 and inductance of leakage inductance 5d. Thus, it is possible in the converter to produce necessary DC electric power from second secondary winding 5c of transformer 5 through second rectifying smoother 17 independently of fluctuation in load occurred on the side of first secondary winding 5b of transformer 5.
FIG. 6 is a graph exhibiting a variation in first DC output voltage VO1 on the secondary side with change in the on-period ratio or duty ratio of first MOS-FET 2 to second MOS-FET 3 in prior art DC-DC converter of multi-output type shown in FIG. 1. FIG. 6 displays that first DC output voltage VO1 from first output terminals 10 and 11 can be adjusted by changing the on-period ratio of first MOS-FET 2 to second MOS-FET 3 in a range from 0.3 to 1.0. Specifically, the on-period ratio of first and second MOS-FETs 2 and 3 can be varied to adjust charged voltage VC2 of current resonance capacitor 4 for control of voltage applied on primary winding 5a of transformer 5 so that first DC output voltage VO1 from first DC output terminals 10 and 11 can be appropriately regulated.
First output voltage detector 12 picks out first DC output voltage VO1 available from first DC output terminals 10 and 11 to produce error signal VE1, the differential between output voltage VO1 and limitary reference voltage so that error signal VE1 is transmitted to input terminal FB of primary control circuit 14 as a feedback signal through light emitter 13a and receiver 13b of photocoupler 13. Then, primary control circuit 14 prepares first and second drive signals VG1 and VG2 whose pulse frequencies are modulated (PFM or Pulse Frequency Modulation) based on voltage level of error signal VE1 forwarded from first output detector 12 to input terminal FB, and applies them to each gate terminal of first and second MOS-FETs 2 and 3 which are then alternately turned on and off with the operating frequency corresponding to voltage level of error signal VE1 from first output detector 12. Specifically, with higher output voltage VO1, error signal VE1 has the higher voltage level to reduce the operating frequency, thereby causing output voltage VO1 to fall down, adversely, with lower output voltage VO1, error signal VE1 has the lower voltage level to increase the operating frequency, thereby causing the output voltage VO1 to rise. In this way, first DC output voltage VO1 produced from first output terminals 10 and 11 can be controlled toward and maintained at a substantially constant value.
When first MOS-FET 2 is turned on, a voltage is generated on primary winding 5a of transformer 5 to simultaneously induce voltage VT22 on second secondary winding 5c of transformer 5, second rectifying smoother 17 and timing detector 29 in secondary control circuit 21. At the moment, timing detector 29 delivers detection signal VTD of high voltage level to set terminal S of RS flip flop 32 and PWM control circuit 31 to set RS flip flop 32 and drive PWM control circuit 31. Accordingly, RS flip flop 32 produces from output terminal Q the output signal to drive circuit 33 which in turn provides secondary drive signal VS2 of high voltage level for gate terminal of output control MOS-FET 20 to turn on MOS-FET 20. This causes current flow ID2 to run from second secondary winding 5c of transformer 5 through second output rectifying diode 15 to second output smoothing capacitor 16 of second rectifying circuit 17 to charge capacitor 16 and raise output voltage VO2.
When output control MOS-FET 20 is turned on, voltage VT22 on second secondary winding 5c is clamped with voltage VO2 of smoothing capacitor 16 to apply on leakage inductance 5d, the differential voltage deducted the voltage equivalent to turn ratio of primary and second secondary windings 5a and 5c from voltage applied on leakage and excitation inductances 5d and 5e of transformer 5. In the exemplified DC-DC converter illustrated in FIG. 1, leakage inductance 5d of transformer 5 can serve to absorb unnecessary potential component of output voltage. Subsequently, output control MOS-FET 20 is turned off to release voltage clamp on second secondary winding 5c so that produced on first secondary winding 5b is a common voltage which is clamped with first output voltage VO1 on first output smoothing capacitor 8. Thus, during the on-period of first primary MOS-FET 2, current flow ID2 runs through second output rectifying diode 15 of second rectifying smoother 17, and after turning off of output control MOS-FET 20, current flow ID1 runs through first output rectifying diode 7 of first rectifying smoother 9. In case there is little potential difference between first and second DC output voltages VO1 and VO2, current flows ID1 and ID2 may simultaneously pass through respectively first and second output rectifying diodes 7 and 15 by ripple voltages from respectively first and second output rectifying capacitors 8 and 16. Here, FIGS. 7(A) to 7(G) represent waveforms of voltage VQ2 between source and drain terminals of second primary MOS-FET 3, current flow IQ2 through second primary MOS-FET 3, voltage VQ1 between drain and source terminals of first MOS-FET 2, current flow IQ1 through first MOS-FET 2, current flow ID1 through first output rectifying diode 7, current flow ID2 through second output rectifying diode 15 and voltage VC2 produced across current resonance capacitor 4.
Meanwhile, second output voltage detector 30 in secondary control circuit 21 senses second output voltage VO2 across second output smoothing capacitor 16 of second rectifying smoother 17 so that second detector 30 prepares error signal VE2 between detection signal VO2 and limitary reference voltage, and forwards error signal VE2 to PWM control circuit 31. Driven by detection signal VTD of high voltage level supplied from timing detector 29 is PWM control circuit 31 which outputs pulse array signal VPT to reset terminal of RS flip flop 32 and thereby controls duty ratio of pulse array signal VPT based on voltage level of error signal VE2 from second output voltage detector 30. In detail, when second output voltage VO2 from second output smoothing capacitor 16 is higher than reference voltage, PWM control circuit 31 produces pulse array signal VPT of small duty ratio, on the contrary, when second output voltage VO2 is lower than reference voltage, PWM control circuit 31 produces pulse array signal VPT of large duty ratio. Accordingly, when second DC output voltage VO2 is above a set value, PWM control circuit 31 produces pulse array signal VPT of small duty ratio to reset terminal R of RS flip flop 32 to apply secondary drive signal VS2 of narrow pulse width from output terminal Q of RS flip flop 32 through drive circuit 33 to gate terminal of output control MOS-FET 20. Secondary drive signal VS2 of narrow pulse reduces the on-period of output control MOS-FET 20 to terminate early on or shorten the period for allowing charge current to flow into second output smoothing capacitor 16, thus lowering second output voltage VO2 from second output smoothing capacitor 16. On the contrary, when second DC output voltage VO2 is below the set value, PWM control circuit 31 produces pulse array signal VPT of large duty ratio to reset terminal R of RS flip flop 32 to apply secondary drive signal VS2 of wide pulse width from output terminal Q of RS flip flop 32 through drive circuit 33 to gate terminal of output control MOS-FET 20. Secondary drive signal VS2 of wide pulse extends the on-period of output control MOS-FET 20 to terminate late or widen the period for allowing charge current to flow into second output smoothing capacitor 16, thus boosting second output voltage VO2 from second output smoothing capacitor 16. In this way, the on-period of output control MOS-FET 20 can be controlled based on second output voltage VO2 from second rectifying smoother 17 synchronously with the on-period of first primary MOS-FET 2 to adjust second DC output voltage VO2 between second output terminals 18 and 19 to a substantially constant value.
Japanese Patent Disclosure No. 3-7062 exhibits a switching power source of resonance type which comprises a frequency modulator for performing frequency modulation of reference pulse signals to produce pulse array signals; a power transistor on the primary side to be turned on and off by pulse array signals for controlling voltage applied on a primary winding of a transformer; a plurality of secondary windings electromagnetically connected to the transformer; and a rectifying smoother for rectifying and smoothing an output from each secondary winding. In this switching power source, a comparator as a primary control means controls frequency of pulse array signals delivered from frequency modulator in response to output signals from a predetermined rectifying smoother on the secondary side. Also, a secondary switching transistor is turned on and off by secondary control circuit in response to outputs from a secondary winding through a rectifying smoother to control the duty cycle in pulse array voltage produced on the output side of the secondary switching transistor. Controlling the duty cycle thins an appropriate amount of pulse array voltage produced on the output side of secondary switching transistor to adjust DC output voltages from secondary windings through rectifying smoothers.
On the other hand, Japanese Patent Disclosure No. 2000-295847 demonstrates a transformer for switching power source or inverter which comprises a core, and primary, first secondary and second secondary windings wound in the outward order around the core with an insulating paper between first and second secondary windings. In this transformer, leakage inductance in second secondary winding is greater than that in first secondary winding to reduce ripple current during the switching operation. Also, as magnitude of surge voltage is proportional to ramp of ripple current, inclination of winding current becomes greater when larger ripple current occurs, thereby causing possible larger surge voltage and considerable voltage fluctuation to appear on first secondary winding. In this view, first secondary winding serves to provide a power source for generating drive voltages to such as main switching elements or motor of cooling fan relatively resistible against noise. On the other hand, as small surge voltage occurs on second secondary winding due to the small ripple current, second secondary winding serves to provide a stabler power source with little voltage fluctuation for controllers or interfaces susceptible to surge voltage. Although large surge voltage may occur on first secondary winding, electric power can be transmitted from the primary side to first secondary winding with high transmission efficiency due to the small leakage inductance. As mentioned above, in the converter shown in FIG. 1, electric powers can be obtained from each of secondary windings for suitable applications in view of magnitude of their leakage inductances with higher transmission efficiency than that in a transformer having secondary windings all of which involve large leakage inductance. The converter also is advantageous in that it has a simplified structure of filter circuits to provide an inexpensive power source.
However, prior art DC-DC converter shown in FIG. 1 or switching power source described in Japanese Patent Disclosure No. 3-7062 are defective in that they may involve serge voltage arisen on second secondary winding 5c from inductance of second secondary winding 5c when output control MOS-FET 20 is turned off, since second output current ID2 intermittently flows through second secondary winding 5c of transformer 5 by turning on and off of secondary output control MOS-FET 20. In addition, as shown in FIG. 2 or in Japanese Patent Disclosure No. 2000-295847, in some cases, first and second secondary windings 5b and 5c are concentrically wound adjacently to each other through insulating paper to form an electromagnetically close coupling between first and second secondary windings 5b and 5c so that serge voltage occurred on second secondary winding 5c leads to induce associated serge voltage on first secondary winding 5b. In particular, when first secondary winding 5b is connected to load through first DC output terminals 10 and 11 under the light- or no-load condition, electric energy supplied to load may include relatively indispensable amount of serge voltage to increase first output voltage VO1 through first rectifying smoother 9 by the amount equivalent to serge voltage. First output voltage detector 12 picks out increased first output voltage VO1 and transmits it as a feedback signal to input terminal FB of primary control circuit 14 through photocoupler 13 so that primary control circuit 14 controls the on-period of first and second primary MOS-FETs 2 and 3 to restrict electric power supplied from primary to secondary side. For example, primary control circuit 14 controls the on-period of first and second primary MOS-FETs 2 and 3 based on feedback signal to input terminal FB to make first output voltage VO1 generated on first secondary winding 5b decrease by increased amount resulted from serge voltage so as to still return and keep first DC output voltage VO1 at a constant level. On the other hand, second DC output voltage VO2 between second DC output terminals 18 and 19 is diminished accordingly by an equivalent amount to decreased voltage in first secondary winding 5b. In this way, the prior art converter is disadvantageous in that second DC output voltage VO2 is inconveniently made step-down or fluctuant upon occurrence of serge voltage under the light- or no-load condition, and this unstable output voltage obviously impedes ideal cross-regulation to all DC outputs.
An object of the present invention is to provide a DC-DC converter of multi-output type capable of producing a plurality of stable outputs throughout the entire loaded and unloaded range.